The present invention relates to a semiconductor device and a manufacturing method thereof, particularly to a semiconductor device having a metal resistor layer and a manufacturing method of the device.
Microcomputer products and oscillators have conventionally been provided as separate structures. In recent years, oscillators have been integrated in microcomputer chips for the purpose of narrowing a layout area, reducing a production cost, or the like. To achieve integration of oscillators in microcomputer chips, stable output of an oscillation frequency under any environment (voltage/temperature) is necessary. High-speed OCO (on chip oscillator) circuits of microcomputer products are therefore required to achieve, for example, 40 MHz±1% as target accuracy.
As a resistor of a constant current generator circuit in the high-speed OCO (on chip oscillator) circuit which is an analog circuit, a polysilicon resistor is used. Due to a so-called piezoresistive effect, however, the resistance of the polysilicon resistor varies depending on a stress. In particular, resistance varies remarkably depending on a mold stress in and after a packaging step. The frequency of the high-speed OCO circuit therefore varies greatly and as a result, it may be difficult to achieve the target accuracy of the high-speed OCO circuit.
As a prior art document, Patent Document 1 discloses an oscillator circuit capable of narrowing a layout area, reducing dependency on a power supply voltage, and reducing a rise time at the time of startup. This circuit is realized by a constant current circuit using a low-resistance resistor.
As another prior art document, Patent Document 2 discloses a semiconductor integrated circuit having a structure not causing a variation in the set value of a detection voltage even when resistance changes due to a piezoresistive effect which occurs depending on a mold stress unevenly distributed on the chip.
As a further prior document, Patent Document 3 discloses a semiconductor device having a configuration capable of, upon exposure in photolithography to define the formation position of a metal resistor, preventing generation of a standing wave in the resist film and thereby reducing the dimensional variation of the metal resistor.
As a still further prior document, Patent Document 4 discloses a semiconductor device with a resistor featuring a low parasitic capacitance and small variations of resistance due to heat treatment.
[Patent Document 1] Japanese Patent Laid-Open No. 64699/1997
[Patent Document 2] Japanese Patent Laid-Open No. 17113/1999
[Patent Document 3] Japanese Patent Laid-Open No. 2008-251616
[Patent Document 4] Japanese Patent Laid-Open No. 2009-021509